;buildInfoPackage: chisel3, version: 3.1.8, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2019-07-08 17:44:42.884, builtAtMillis: 1562607882884
circuit GCD : 
  module GCD : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<16>, flip b : UInt<16>, flip e : UInt<1>, z : UInt<16>, v : UInt<1>}
    
    reg x : UInt, clock @[GCD.scala 16:15]
    reg y : UInt, clock @[GCD.scala 17:15]
    node _T_17 = gt(x, y) @[GCD.scala 18:13]
    when _T_17 : @[GCD.scala 18:18]
      node _T_18 = sub(x, y) @[GCD.scala 18:27]
      node _T_19 = asUInt(_T_18) @[GCD.scala 18:27]
      node _T_20 = tail(_T_19, 1) @[GCD.scala 18:27]
      x <= _T_20 @[GCD.scala 18:22]
      skip @[GCD.scala 18:18]
    else : @[GCD.scala 19:24]
      node _T_21 = leq(x, y) @[GCD.scala 19:18]
      when _T_21 : @[GCD.scala 19:24]
        node _T_22 = sub(y, x) @[GCD.scala 19:33]
        node _T_23 = asUInt(_T_22) @[GCD.scala 19:33]
        node _T_24 = tail(_T_23, 1) @[GCD.scala 19:33]
        y <= _T_24 @[GCD.scala 19:28]
        skip @[GCD.scala 19:24]
    when io.e : @[GCD.scala 20:15]
      x <= io.a @[GCD.scala 20:19]
      y <= io.b @[GCD.scala 20:30]
      skip @[GCD.scala 20:15]
    io.z <= x @[GCD.scala 21:8]
    node _T_26 = eq(y, UInt<1>("h00")) @[GCD.scala 22:13]
    io.v <= _T_26 @[GCD.scala 22:8]
    
